Heterojunction bipolar transistors (HBTs) exhibit desirable features such as high power density and an extremely high cut-off frequency as compared to other devices like MESFETs. Even so, HBTs intended for microwave power applications require ever-increasing power gain and efficiency. It is well-known that power gain is inversely proportional to base-collector capacitance. Hence, a transistor that has its base-collector capacitance reduced by a factor of two can produce approximately 3 dB more in power gain.
Previous partial solutions addressing this base-collector capacitance have tended to produce transistors with inferior performance because the process of reducing base-collector capacitance often results in an increase in other parasitic impedances. For example, one simple method of reducing base-collector capacitance is to minimize the base contact area. However, this involves a design tradeoff between base resistance, which improves with increasing contact area, and junction capacitance, which degrades with increasing contact area. Another past effort was the ion bombardment of the extrinsic base region (see Japanese Patent No. 2-235341). Ion bombardment reduces the effective doping density of the layer beneath the base in the extrinsic base region. At best, this approach ensures that the collector layer beneath the extrinsic base is depleted of free carriers. This increases the effective dielectric thickness between the base and the underlying subcollector, thereby reducing the capacitance between those layers. A disadvantage of the ion bombardment approach is that the bombardment of the base layer results in increased base resistance. In addition, this technique requires great sensitivity, as it may result in reduced device reliability and degraded device current gain. Another problem is that it only reduces zero-bias base-collector capacitance.
Another approach taken in the prior art has been to include a layer in the material structure next to the collector layer. This layer is of a material that allows it to be easily removed without removing the surrounding material. In other words, the layer may be selectively etched. An example of this approach is shown in FIG. 1, where the transistor is an emitter-up type that is fabricated on a monolithic semiconductor substrate 20. The transistor comprises an emitter mesa 30 and emitter contact 32 over base 28 and collector 26 layers. The transistor shown includes an etch layer 24 between the subcollector 22 and the collector 26 layers. The etch layer allows the area of the interface between the lightly doped collector layer 26 and the highly doped subcollector layer 22 to be decreased. This also has the effect of lowering the overall base-collector capacitance. The problem with this approach is that it is difficult to reproducibly perform the selective etch so that the degree of undercut is the same across a semiconductor wafer or from wafer to wafer. In addition, the ledge comprising the base layer 28 and base contact 34, and that overhangs the undercut region, is prone to breakage in subsequent processing steps. The present invention is intended to address these problems.